The present invention is directed to the field of carrier lock detectors for detecting phaselock conditions in four-phase PSK demodulators. One method of transmitting digital data between locations is the four-phase PSK method wherein data bits are paired and used to modulate two carrier signals, which signals are of the same frequency but displaced in phase. PSK modulation causes a change in the relative phase of the carrier signal. As an example, if the data bit is binary in form, the carrier signal may have a relative phase of either 0.degree. or 180.degree. depending upon whether a binary 1 or a binary 0 is to be transmitted respectively. In a four-phase PSK system the second carrier signal is shifted 90.degree.; therefore it will have a relative phase of either +90.degree. or - 90.degree. depending upon whether a binary 1 or a binary 0, respectively, is to be transmitted. The two modulated carrier signals are combined to generate a single carrier signal which contains data in the form of phase shifts.
Demodulation of the modulated carrier signal is accomplished in the receiver by comparing the phase of the modulated carrier with that of a reference signal having the same frequency and some fixed relationship with respect to the modulated carrier. Generally speaking then, the output signals from the demodulators are compared in a phaselock loop circuit wherein a control signal is generated, which signal is proportional to the difference in phase between the phase of the local oscillator and the modulated carrier signal. The signal from the phaselock loop is used to place the phase of the local oscillator into some fixed phase relationship with respect to the carrier signal. In a number of prior art systems the phasing of the local oscillator signal is synchronized with the phase of the modulated carrier signals. Demodulation then is accomplished through synchronous detection, which detection is also known by the term homodyne detection. If the local oscillator is not locked in a fixed relationship with respect to the modulated carrier signal an error will occur in the detection of the modulating data. It therefore becomes desirable to have a means whereby an out-of-lock condition, or an in-lock condition is indicated, so as to enable an operator of the system to determine if valid data is being received versus, for example, invalid data.
A prior art patent of interest is U.S. Pat. No. 3,456,196, entitled "Digital Automatic Frequency Control System," by H. A. Schneider. In the aforementioned patent there is disclosed a device wherein an incoming double sideband suppressed carrier signal is mixed with the voltage from a local voltage tuned oscillator to produce a pair of quadrature demodulated signals. A translator is used to provide signals indicative of the difference between the carrier and the local oscillator signal. A difference counter compares the digital pulses, and provides a count which is indicative of the difference. The provided count is then converted into an analog signal for control of the voltage oscillator. A locked indicator circuit is used to monitor the output signal of the difference counter to indicate when phaselock is obtained. Two signal channels are provided within the locked monitor, each channel consisting of an OR gate, a single shot multivibrator, and a peak detector. The lock indicator receives signals from two portions of the receiver circuit in order to accurately determine when a locked condition exists versus, for example, a condition of receiving no signal at all.
The present inventive carrier lock detector does not require the services of a difference counter or a translator in order to indicate the condition of loop phaselock.
Another prior art patent of interest is U.S. Pat. No. 3,525,945, entitled, "System For Reconstituting A Carrier Reference Signal Using A Switchable Phaselock Loop," by J. G. Puente. The lock detector described in the patent operates by comparing the output signal from a phaselock loop against the signal being fed to the phaselock loop. If the two signals are in phase, a multiplier output signal will be at maximum value which value will be greater than a determined threshold level. By utilizing a threshold detector set at the determined threshold level the device provides an output signal when the product signal is above the threshold level to thereby indicate a locked condition. The present invention, unlike the foregoing device, does not require a comparison of the output signal from the phaselock loop in order to make a determination as to whether or not there is a condition of phaselock.